MOS Amplifier Structures

This article details the structures of basic mos amplifiers.

Common Source

CS with Resistor Load

In saturation mode, the voltage gain is

$$\begin{aligned} A_v&=-R_D\mu_nC_{ox}\frac{W}{L}(V_{in}-V_{TH})\\ &=-g_mR_D \end{aligned}$$

In triode mode, the voltage gain is

$$\begin{aligned} A_v&=\frac{-\mu_nC_{ox}(W/L)R_DV_{out}}{1+\mu_nC_{ox}(W/L)R_D(V_{in}-V_{TH}-V_{out})} \end{aligned}$$

which reaches maximal when $V_{out}=V_{in}-V_{TH}$.

CS with Diode Load (Cascode)

A diode can be realized by connecting the gate and drain of a transistor

In that case, the equivalent output resistance is

$$r_{eq}=\frac{1}{g_m+g_{mb}}||r_o$$

From a large-signal perspective, a diode act like a "square root" operator.

The voltage gain of a CS stage with diode load is

$$\begin{aligned} A_v&=-g_{m1}\left(\frac{1}{g_{m2}+g_{mb2}}||r_{o1}||r_{o2}\right)\\ &\approx-\sqrt{\frac{(W/L)_1}{(W/L)_2}}\frac{1}{1+\eta} \end{aligned}$$

where $\eta=g_{mb2}/g_{m2}$

The working state of this configuration is

1. $V_{in}<V_{TH1}, V_{out}\approx V_{dd}-V_{TH2}$, M1 off, M2 near cut-off
2. $V_{TH1}<V_{in}<V_{out}+V_{TH1}$, M1 saturation, M2 saturation, linear
3. $V_{out}+V_{TH1}<V_{in}$, M1 diode, M2 saturation

Strong input device and weak load device can lead to high gain, yet the voltage swing is severely limited.

CS with Current-Source Load

Assume that M2 is operating in saturation region.

The voltage gain is

$$A_v=-g_{m1}(r_{o1}||r_{o2})$$

CS with Active Load

The voltage gain is

$$A_v=-(g_{m1}+g_{m2})(r_{o1}||r_{o2})$$

This topology is sensitive to PVT variation due to $V_{GS1}+V_{GS2}=V_{DD}$. Still, it would amplify supply noise, the gain is

$$\frac{V_{out}}{V_{DD}}=\left(g_{m2}+\frac{1}{r_{o2}}\right)(r_{o1}||r_{o2})$$

CS with Triode Load

Assume that M2 is operating in deep triode region and behaves as a resistor ($V_b$ is very close to $V_{DD}$).

The voltage gain is

$$A_v=-g_{m1}(r_{o1}||R_{on2})\\ R_{on2}=\frac{1}{\mu_pC_{ox}\frac{W}{L}(V_{DD}-V_{b}-|V_{THP}|)}$$

This circuit is difficult to provide bias with consideration to PVT variation. However, as compared to diode counterpart, it has no output voltage headroom (i.e. $V_{out,max}=V_{DD}$)

CS with Source Degeneration

Like diode load, source degeneration can be employed to enhance the linearity.

$$\begin{aligned} A_{v}&=\frac{-g_mR_D}{1+g_mR_S}\\ &=-\frac{R_D}{\frac{1}{g_m}+R_S} \end{aligned}$$

This can be explained as "the resistance seen at the drain" divided by "the total resistance in the source path".

$$G_m=\frac{g_mr_o}{R_S+[1+(g_m+g_{mb})R_S]r_o}$$

• When $V_{in}$ is low, $1/g_m\gg R_s, G_m\approx g_m$
• For large $V_{in}$, $1/g_m\ll R_s, G_m\approx 1/R_s$

As depicted from the figure, the large signal gain is relatively smooth with source degeneration.

The output impedance is

$$R_{out}=[1+(g_m+g_{mb})R_S]r_O+R_S$$

The gain can be written as

$$\begin{aligned} A_v&=\frac{-g_mr_OR_D}{R_D+R_S+r_O+(g_m+g_{mb})R_Sr_O}\\ &=G_m\cdot(R_{out}||R_D) \end{aligned}$$

Source Follower

Source follower can act like a buffer. It offers high input resistance and low output resistance.

$$\begin{aligned} A_v&=\frac{g_mR_S}{1+(g_m+g_{mb})R_S}\\ &=\frac{(\frac{1}{g_{mb}}||R_S)}{\frac{1}{g_m}+(\frac{1}{g_{mb}}||R_S)}\\ &=\frac{R_{eq}}{\frac{1}{g_m}+R_{eq}} \end{aligned}$$

With a current source rather than a resistor as load, the linearity can be improved because $V_{GS}$ will be fixed for a fixed $I_d$.

$$R_{out}=\frac{1}{g_m+g_{mb}}$$

Common Gate

$$A_v=(g_m+g_{mb})R_D\\ R_{in}=\frac{1}{g_m+g_{mb}}$$

A more detailed calculation of Av reveals

$$A_v=\frac{(g_m+g_{mb})r_o+1}{r_o+(g_m+g_{mb})r_oR_S+R_S+R_D}R_D$$

For a more detailed calculation of Rin

$$R_{in}=\frac{R_D+r_o}{1+(g_m+g_{mb})r_o}\\ R_{out}=\{[1+(g_m+g_{mb})r_o]R_s+r_o\}||R_D$$

The MOS can transform impedance up from source to drain, or down from drain to source.

Cascode

For both MOS to be in saturation

$$V_{out} \ge (V_{GS1}-V_{TH1})+(V_{GS2}-V_{TH2})$$

The large signal operating mode is as follows:

• For $V_{in}<V_{TH1}$, M1 off, M2 off, $V_{out}=V_{DD}$
• For $V_{in}>V_{TH1}$, M1 saturation, M2 saturation
• For sufficiently large $V_{in}$, two occasions can occur
  • M1 enter triode region first
  • M2 enter triode region first

Neglecting channel length modulation effect, Cascode amplifier has gain of

$$A_v=-G_{m}R_{out}\\ R_{out}=[1+(g_{m2}+g_{mb2})r_{o2}]r_{o1}+r_{o2}$$

Cascode can reduce mismatch because

In the first case

$$\Delta I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_b-V_{TH})^2(\lambda\Delta V)$$

Instead, in the second case

$$V_{PQ}=\Delta V\frac{r_{o1}||\frac{1}{g_{m3}+g_{mb3}}}{r_{o3}+(r_{o1}||\frac{1}{g_{m3}+g_{mb3}})}\\ \Delta I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_b-V_{TH})^2\frac{\lambda\Delta V}{(g_{m3}+g_{mb3})r_{o3}}$$

Folded Cascode is as follows:

• Higher DC consumption for comparable performance

Miller Effect

The current flowing from X to Y is

$$\frac{V_X-V_Y}{Z}=\frac{V_X}{Z_1}$$

Therefore

$$Z_1=\frac{Z}{1-\frac{V_Y}{V_x}}=\frac{Z}{1-A_v}$$

Similarly

$$Z_2=\frac{Z}{1-\frac{V_Y}{V_X}}=\frac{Z}{1-1/A_v}$$

Attention:

• Only actual $A_v$ at the frequency of interest may be used to accurately predict the input impedance, but low-frequency $A_v$ is useful for approximation (it may eliminate zeros and predict additional poles).
• Since the reverse gain is not necessarily $1/A_v$ (as in the case of CG), it cannot be used to calculate the output impedance directly. Instead, a voltage source should be connected at the output node to test the reverse gain, and that result be used to calculate the impedance.
• Trans-impedance Z must present in the process of calculating $A_v$.

Frequency Response

Association of Poles with Nodes

We can associate each pole with one node of the circuit. It is not always true, but affords an intuitive approach to the estimation of the transfer function.

General Formula

$$A_v(s)=A_v(0)\frac{1}{(1+sR_1C_1)(1+sR_2C_2)...}$$

Common Source

Poles can be estimated as

$$\omega_{in}=\frac{1}{R_S[C_{GS}+(1+g_mR_D)C_{GD}]}\\ \omega_{out}=\frac{1}{R_D(C_{DB}+C_{GD})}$$

and the gain is

$$A_v(s)=\frac{-g_mR_D}{\left(1+\frac{s}{\omega_{in}}\right)\left(1+\frac{s}{\omega_{out}}\right)}$$

A direct analysis shows

$$A_v(s)=\frac{R_D(sC_{GD}-g_m)}{\xi s^2+\varepsilon s+1}\\ \xi=R_sR_D(C_{GS}C_{GD}+C_{GS}C_{DB}+C_{GD}C_{DB})\\ \varepsilon=R_S(1+g_mR_D)C_{GD}+R_SC_{GS}+R_D(C_{GD}+C_{DB})$$

The denominator can be written as

$$\begin{aligned} D&=\left(\frac{s}{\omega_{p1}}+1\right)\left(\frac{s}{\omega_{p2}}+1\right)\\ &=\frac{s^2}{\omega_{p1}\omega_{p2}}+\left(\frac{1}{\omega_{p1}}+\frac{1}{\omega_{p2}}\right)s+1 \end{aligned}$$

Further assume that $1/\omega_{p2}\ll1/\omega_{p1}$, we have

$$\omega_{p1}=\frac{1}{\varepsilon}\approx\omega_{in}\\ \omega_{p2}=\frac{1}{\omega_{p1}\xi}$$

A zero exists as

$$\omega_z=\frac{g_m}{C_{GD}}>\frac{g_m}{C_{GS}}=f_T$$

Signal cancellation model is as follows:

Source Follower

Strong interaction through $C_{GS}$ makes it difficult to associate a pole with each node in the circuit. Calculation shows

$$A_v(s)=\frac{g_m+C_{GS}s}{\xi s^2+\varepsilon s+g_m}\\ \xi=R_s(C_{GS}C_{L}+C_{GS}C_{GD}+C_{GD}C_{L})\\ \varepsilon=g_mR_SC_{GD}+C_{L}+C_{GS}$$

Therefore

$$\omega_{p1}\approx\frac{g_m}{\varepsilon}$$

Note if $C_L=0$, the previous formula reduces to

$$A_v(s)=\frac{1}{1+R_SC_{GD}s}$$

In this case, only one pole at the input presents. We say $C_{GS}$ is bootstrapped by the source follower.

Neglecting channel length modulation, the input impedance is

$$\begin{aligned} Z_{in}&=\frac{1}{C_{GS}s}+\frac{1}{C_{GD}s}+\left(1+\frac{g_m}{C_{GS}s}\right)\frac{1}{g_{mb}+C_Ls}\\ &\approx\frac{1}{C_{GD}s}+\frac{1}{C_{GS}s}\left(1+\frac{g_m}{g_{mb}}\right)+\frac{1}{g_{mb}} &\text{low}\ f\\ &\approx\frac{1}{C_{GD}s}+\frac{1}{C_{GS}s}+\frac{1}{C_{L}s}+\frac{g_m}{C_{GS}C_{L}s^2} &\text{high}\ f \end{aligned}$$

It presents negative real input impedance at high frequency, thus is possibly unstable.

Output impedance is

$$\begin{aligned} Z_{out}&=\frac{R_SC_{GS}s+1}{g_m+C_{GS}s}\\ &\approx 1/g_m &\text{low}\ f\\ &\approx R_s &\text{high}\ f\\ \end{aligned}$$

Figure (c) is more common, as when operated as buffer, $Z_{out}<Z_{in}$. It can be modelled as

$$R_2=1/g_m\\ R_1=R_S-1/g_m\\ L=\frac{C_{GS}}{g_m}\left(R_S-\frac{1}{g_m}\right)$$

Thus, source follower can be used to realize inductors.

Common Gate

We have

$$\omega_{in}=\frac{1}{(C_{GS}+C_{SB})(R_S||\frac{1}{g_m+g_{mb}})}\\ \omega_{out}=\frac{1}{(C_{GD}+C_{DB})R_D}\\ A_v(s)=\frac{(g_m+g_{mb})R_D}{1+(g_m+g_{mb})R_S}\cdot\frac{1}{\left(1+\frac{s}{\omega_{in}}\right)\left(1+\frac{s}{\omega_{out}}\right)}$$

It has no Miller multiplication of capacitances, thus have wider bandwidth.

Cascode

The pole associated with node A is

$$\omega_{p,A}=\frac{1}{R_S\left[C_{GS1}+\left(1+\frac{g_{m1}}{g_{m2}+g_{mb2}}\right)C_{GD1}\right]}$$

The pole associated with node X is

$$\omega_{p,X}=\frac{g_{m2}+g_{mb2}}{\left(1+\frac{g_{m2}+g_{mb2}}{g_{m1}}\right)C_{GD1}+C_{DB1}+C_{SB2}+C_{GS2}}$$

The pole associated with node Y is

$$\omega_{p,Y}=\frac{1}{R_D(C_{DB2}+C_{L}+C_{GD2})}$$

Extra Element Theorem

Zero Value Time Constant Method

The dominant pole of a circuit equals to the sum of all zero value time constants, each of which is obtained by setting input voltage and other capacitance to zero and computing the product of the capacitance of interest and its corresponding equivalent resistance.

Proof

1. The dominant pole is the coefficient of $s$ in the denominator.

   Denominator can be written as

   $$D(s)=\left(1+\frac{s}{\omega_{p1}}\right)\left(1+\frac{s}{\omega_{p2}}\right)...\left(1+\frac{s}{\omega_{pn}}\right)$$

   Therefore, the coefficient of $s$ is $\omega_{p1}^{-1}+\omega_{p2}^{-1}+...+\omega_{pn}^{-1}$, which reduce to $\omega_{p1}^{-1}$ with dominant pole assumption.

2. The coefficient of $s$ in the denominator equals to the sum of all zero-value time constants.

   Since the coefficient of $s$ has a time dimension, we can write it as $B_s=R_1C_1+R_2C_2+...+R_nC_n$, where $C_1-C_n$ denote real capacitors, and $R_1-R_n$ are unknown. With $C_2-C_n$ set to 0, the order of the system reduces to 1, and therefore $R_1$ is the resistance seen by $C_1$.

Reference

1. Behzad Razavi. Design of analog CMOS integrated circuits.