Basic Theory of MOSFETs

This article presents the formulas and theories regarding the basic MOSFETs.

I-V Characteristic

1. Turn-off region ($V_{GS}<V_{TH}$)

2. Triode region/ Linear region ($V_{GS}>V_{TH}, V_{DS}<V_{GS}-V_{TH}$)

   $$I_d=\mu_nC_{ox}\frac{W}{L}\left[(V_{GS}-V_{TH})V_{DS}-\frac{1}{2}V_{DS}^2\right]$$

3. Saturation region/ Square law ($V_{GS}>V_{TH}, V_{DS}>V_{GS}-V_{TH}$)

   $$I_d=\frac{1}{2}\mu_nC_{ox}\frac{W}{L'}\left(V_{GS}-V_{TH}\right)^2$$

Calculation of Gm

In saturation region

$$\begin{aligned} g_m&=\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})\\ &=\sqrt{2\mu_nC_{ox}\frac{W}{L}I_D}\\ &=\frac{2I_D}{V_{GS}-V_{TH}} \end{aligned}$$

Second-Order Effects

Body Effect

$$V_{TH}=V_{TH0}+\gamma\left(\sqrt{2\Phi_F+V_{SB}}-\sqrt{|2\Phi_F|}\right)$$

and

$$\gamma=\frac{\sqrt{2q\epsilon_{si}N_{sub}}}{C_{ox}}\\ V_{TH0}=\Phi_{MS}+2\Phi_{F}+\frac{Q_dep}{C_ox}\\ Q_{dep}=\sqrt{4q\epsilon_{si}|\Phi_F|N_{sub}}\\ \Phi_F=\frac{kT}{q}\ln{\frac{N_{sub}}{n_i}}$$

Thus, body effect can be utilized to modify the threshold voltage.

Channel Length Modulation

$$I_d=\frac{1}{2}\mu_nC_{ox}\frac{W}{L'}\left(V_{GS}-V_{TH}\right)^2(1+\lambda V_{DS})$$

and

$$\lambda\propto\frac{1}{L}$$

Thus, long-channel MOSFET exhibits less channel modulation effect.

Subthreshold Conduction

Or called weak inversion region.

$$I_D=I_0\exp\frac{V_{GS}}{\xi V_{T}}$$

and

$$V_{T}=\frac{kT}{q}$$

MOSFETS operating in subthreshold region have higher gain, but generally, MOSFETs are inferior to bipolar transistors in terms of gm.

Parasitic

Capacitance

$$C_1=WLC_{ox}\\ C_2=WL\sqrt{q\epsilon_{si}N_{sub}/(4\Phi_F)}\\ C_{5/6}=C_j+C_{jsw} C_j=C_{j0}/[1+V_R/\Phi_B]^m$$

1. Off region

   $$C_{GS}=C_{GD}=C_{3/4}=WC_{ov}\\ C_{GB}=\frac{C_1C_2}{C_1+C_2}$$

2. Triode region

   Gate-channel capacitance is evenly split between the source and the drain

   $$C_{GS}=C_{GD}=\frac{C_{1}}{2}+C_{3/4}$$

3. Saturation region

   $$C_{GD}=C_{3/4}=WC_{ov}\\\\ C_{GS}=\frac{2}{3}C_1+C_{3/4}$$

Resistance

In saturation region

$$\begin{aligned} r_o&=\frac{\partial V_{DS}}{\partial I_{D}}\\ &=\frac{1}{\frac{1}{2}\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})^2\cdot\lambda}\\ &\approx\frac{1}{\lambda I_D} \end{aligned}$$

In triode region

$$r_{ds}=\frac{1}{\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})}$$

MOSFET as Capacitor

The source, drain and the bulk are connected together as a terminal, while the gate is treated as another terminal.

1. Negative potential on gate -> attract holes -> accumulation region -> high capacitance
2. Rise potential on gate -> expel both holes and electrons -> depletion region/ weak inversion region -> low capacitance
3. Gate potential exceed $V_{TH}$ -> attract electrons -> strong inversion region -> high capacitance

Short-Channel Device

Velocity Saturation (Lateral)

Previously, it is assumed that $v=\mu E$, but that is not true for short-channel devices, as shown in the figure

Consider a extreme case that the velocity is fixed to a maximal value, we have

$$I_D=WC_{ox}(V_{GS}-V_{TH})v_{sat}$$

The drain current is, therefore, irrelevant to the channel length and directly proportional to the overdrive voltage.

Another consequence is the early saturation of Id

Furthermore, $g_m$ would be less sensitive to $I_d$ or $V_{GS}$.

Mobility Degradation (Vertical)

The mobility of the charge carriers in the channel also declines as the gate-source voltage and the vertical field increase.

For this reason, we may expect $g_m=\mu C_{ox}(W/L)(V_{GS}-V_{TH})$ would not strictly follow the linear relationship.

Hot Carrier Effects

While the average velocity of carriers saturates at high fields, the instantaneous velocity and hence the kinetic energy of the carriers continue to increase, especially as they accelerate toward the drain. These are called “hot” carriers.

In the vicinity of the drain region, hot carriers may “hit” the silicon atoms at high speeds, thereby
creating impact ionization. As a result, new electrons and holes are generated, with the electrons absorbed by the drain and the holes by the substrate. Thus, a finite drain-substrate current appears. Also, if the carriers acquire a very high energy, they may be injected into the gate oxide and even flow out the gate terminal, introducing a gate current. The substrate and gate currents are often measured to study hot carrier effects.

Layout Considerations

Well Proximity Effect (WPE)

Due to the reflection of the dope implants, the border areas of the n-well receive a different doping density from those in the middle of the n-well.

This problem can be alleviated by drawing a large n-well beyond the devices.

Length of Diffusion (LOD)

Modern MOS devices are surrounded by a shallow “trench” so as to avoid the formation of a channel between adjacent transistors, called "Shallow Trench Isolation" (STI). STI material has different thermal coefficient to the surrounding silicon, generating stress and altering electrical properties.

To alleviate the problem, dummy fingers could be inserted on the sides of the main device to minimize the propagation of the stress.

Reference

1. Behzad Razavi. Design of analog CMOS integrated circuits.